Tungsten metallization by chemical vapor deposition (CVD) has reliability advantages over metallization using aluminum alloys, and CVD tungsten has lower resistivity and better step coverage than tungsten applied by sputtering. CVD tungsten is however generally difficult to etch with good selectivity to layers of resist and oxide. Further, the thick CVD tungsten lines required to achieve low sheet resistance are difficult to planarize with deposited oxide following CVD tungsten patterning and etching.
Recently, a planar multilevel tungsten interconnect technology has been developed in the industry. Following formation of the device and gate level interconnect structures, a dielectric is applied and the surface is made planar ("planarized"). Then contact holes are defined and etched in the dielectric using conventional techniques. These are then filled, for example, using selective chemical vapor deposited (CVD) tungsten. Then more dielectric is deposited, to a thickness equal to the desired metal thickness. The dielectric is coated with Si.sub.3 N.sub.4 ("nitride"), and grooves are lithographically defined where metal interconnect lines are desired. The nitride is then etched, as well as the dielectric which was deposited over the contacts that had been filled with metal. The wafer is then implanted with silicon using an ion acceleration, using the nitride as a mask. The nitride is then removed chemically, leaving grooves where the metal is to be deposited, and heavy silicon dosage only at the bottom of the grooves.
Selective CVD tungsten is then deposited, the deposition occurring only in the grooves where the heavy silicon concentration is present. Thus the grooves are filled with tungsten to a thickness equal to the depth of the groove. This technique eliminates the problem of tungsten etching, and leaves filled the spaces between tungsten metal lines.
The following problems exist with this conventional process. A silicon implantation step of sufficient dosage to support selective CVD tungsten deposition is relatively expensive to perform. The adhesion of tungsten to, for instance, silicon-implanted oxide, is not expected to be good. In addition, the etching of the grooves in the dielectric must be performed without endpoint, leaving open the possibility of etching grooves into underlying circuitry. Finally, the nucleation preference of silicon over the surrounding oxide is not optimum.
From the above, it can be seen that a need has arisen in the industry for an improved planarized selective tungsten metallization system.